Assembly Language
- Low level
- Mnemonics, Label 用以表示CPU指令
- 組譯(assemble)成CPU指令
Instruction set design
- Register
- Data Bus / Address Bus
- Operation / Operand counts
- Literal value
- Flow control
- CISC / RISC
Addressing mode
- Direct
ldr r0, MEM
- Immediate
mov r0, #1
- Register direct
mov r0, r1
- Register indirect
ldr r0, [r1, #4]
(pre-indexed)ldr r0, [r1, #4]!
(auto-indexed)ldr r0, [r1], #4
(post-index, auto post-increment)ldr r0, [r1, r2 LSL #2]
(with scaling)
- PC relative
ldr r0, [PC, #offset]
System software
- Assembler
- Directive 以".“作為開頭
- Pseudo instruction : Alias
- 轉換mnemonics, label以及literal
- Relocation
- 相對位址
Building of GNU
- Build給amd64, target=arm
Segments
- 參見 ELF cheatsheet
- .text : code, r-x
- .data : data, rw- / r-- (rodata/rdata)
- .bss : uninitialized data, rw-
- NX bit
ARM architecture
採用RISC
Endianness (不重要)
Register
- 通用 : r0 ~ r10 (NR只能放在 r7)
- FP : Frame Pointer(x86 RBP), r11
- IP : Intra Pointer, r12
- SP : Stack Poiter, r13
- LR : Link Register, r14
- PC : r15
- CPSR/APSR : Flags, 只有做比較/S做結尾的指令會更新flag
Conditional Execution
- CPU不會知道signed/unsigned/negative, 一切都依賴設定好的Flags
- B / BL(link) / BX(exchange) / BLX
- EQ : ==
- NE : !=
- GT/GE : > / >=
- LT/LE : < / <=
- HS/LS : Higher / Lower (or same)
- HI/LO : Higher / Lower
- MI : +
- PL : -
- VS/VC : overflow / no overflow
Addressing mode
- i++ / ++i的區別
- Pre-Index : 不會更新
ldr r0, [r1, #1]
- Auto-Index : 先更新, 接著做指令
ldr r0, [r1, #1]!
- Post-Index : 做完才更新 (這裡的
r0
會取[r1]
)ldr r0, [r1], #1
Load / Store
- 參見 context switch
- STM/LDM 指令
- IA : 遞增
- DB : 遞減
stm r0, {r1, r2}
: [r0+4]=r1, [r0]=r2ltm r0, {r1, r2}
: r1=[r0], r2=[r0+4]
- push / pop